The ADC integration time should be selected as a multiple of the period of the noise signal (see Frequency Domain Magnitude Plot in the datasheet). The data clock to an ADC should be selected in such a way that the (1/Sample Rate) is a multiple of the period of the noise signal. The relationship between the Data Clock and the Sampling rate of the ADC can be found in the user module data sheet of the corresponding ADC.
For example if you would like to reject 50Hz supply noise from the ADC result, select the ADC's conversion time to be in multiples of 20mS, ie, 20mS, 40mS, 60mS etc. In terms of sample rate this would be 50sps, 25sps, 16.66sps etc.