How are FIFO empty and full flags generated in Cypress FIFO memories?
A FIFO has two ports - one dedicated to writing and one to reading. Each port is addressed by its own counter. The write counter increments after each write operation. Similarly, the read counter increments after each read operation. When the counters are equal, the FIFO is either empty or full. The trick is figuring out whether it is empty or full. The following figure shows the read and write pointer organization:
Figure 1. Read and Write Pointers
The FIFO is empty when the read pointer catches up with the write pointer, and full when the write pointer catches up with read pointer.
One way of accomplishing this is by making each counter one bit wider than required. All counter bits except the MSB are used to address the FIFO array. In this configuration, every location in the FIFO is accessed twice before the counter rolls over. When the MSBs of the write counter equal those of the read counter, the FIFO is empty. When the MSBs are not equal and the actual count value is same, then the FIFO is full. This scheme makes it relatively simple to generate the empty and full flags. Since the FIFO logic prevents additional writes to a full FIFO and also prevents reads from an empty FIFO, the counters can never get further apart than the depth of the FIFO. This prevents reading old data or overwriting new data.