Flow-through dual-ports allow data access without latency. In other words, data from a read is returned on the same clock cycle the read instruction is issued. This is advantageous in applications where access time to a single piece of data is critical. Unfortunately, reading the memory array and returning a value in the same cycle results in a slower operating frequency, and therefore lower device bandwidth. Pipelined dual-ports increase device bandwidth by breaking the read operation into 2 steps. The memory array is accessed during the first clock cycle. The read data is registered and driven to output in the second cycle. As a result, pipelined devices have 1 cycle of latency to read data. However, by breaking the access into 2 steps the clock cycle can be shorted and device bandwidth increased. There is usually no difference in write operations between flow-through and pipelined devices. In future devices, additional pipeline stages may be added. In this case, the read latency will increase to three, four, or more cycles, but this allows continued improvement in device bandwidth.