Flow-through versus Pipelined memory – KBA221475

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    Translation - Japanese: フロースルー対パイプラインメモリ – KBA221475 - Community Translated (JA)


    Question: - What is the difference between flow-through (FT) and pipelined (PL) modes? Which mode should I use? Why are newer dual-ports pipelined only?



    Flow-through dual-port modes allow data access without latency. In other words, data from a read is returned to the same clock cycle and the read instruction is issued. This is an advantage in applications where access time to a data is critical. Unfortunately, reading the memory array and returning a value in the same cycle results in a slower operating frequency, and therefore, lower device bandwidth. Pipelined dual-port modes increase device bandwidth by breaking the read operation into two steps. The memory array is accessed during the first clock cycle. The read data is registered and driven to output in the second cycle. Thus, pipelined devices have one cycle of latency to read data. However, by breaking the access into two steps, the clock cycle can be shorted and device bandwidth increased. There is usually no difference in write operations between flow-through and pipelined devices. In future devices, additional pipeline stages may be added. In this case, the read latency will increase to three, four, or more cycles, allowing continued improvement in device bandwidth.