The input clock of the UART / TX8 / RX8 User Module must be eight times the desired baud rate. The clock can be set from the User Module Settings which can be derived from any of the Clock Dividers (VC1, VC2, VC3 or SysClk) or from Digital Blocks configured as counter, PWM etc.
As an example, the following equation generates a usable baud rate clock using VC1, VC2 and an 8-bit counter module. Values should be chosen to minimum baud rate error.
Counter period = (SysClk/ 8 / baud rate / VC1 divisor / VC2 divisor )