Is it acceptable to use two 16-bit parallel nvSRAM devices in parallel in order to interface with a 32-bit microprocessor data bus?
It is acceptable to use two 16 bit nvSRAM devices for memory width expansion by putting them side by side and accessing them together. The control signals (CE#, WE#, OE#) of both the nvSRAMs should be tied together and connected to the controller’s CE#, WE# and OE# lines respectively. It is also recommended to pull up WE# line using a 5.6K ~ 10K pull up resistor.Pulling up CE# and OE# lines is not necessary for the nvSRAM design although it is common design practice to pull up control signals.
HSB pin of both the nvSRAMs can be tied together and they can be left open if not used. An internal weak pull has been provide on HSB pin to keep this pin to a default logic high state. Adding an externa pull up of 5.6K ~ 10K on HSB line would be nice to have and this will avoid any false triggering on this line due to spurious noise .