Series of write sequences can be had back-to-back. But back to back read/writes is not completely allowed. So, when a read is started, the next clock cycle(preferably two, since it is a Pipelined SRAM) has to be left idle or deselected before starting another write. In your case, since ADSC is continuously low(assuming /CE is always active), the next cycle after a read starts to put out the data. If you are trying to do a write in this cycle by turning off the /OE and driving the data bus, then this data might not be written into the SRAM. This is also not a legal operation. So, in order for a write to be performed after a read, the latest cycle would be the third clock cycle(that too by turning off the /OE to prevent contention) inclusive of the cycle which started the read or more preferably the fourth cycle.