Interrupt latency calculation for PSoC 3

Version 1
    Question: What is the latency for processing an interrupt in PSoC 3?

     

    Answer:

    It is explained in the Interrupts section of PSoC 3 Datasheet.

    1: Interrupt triggered asynchronous to the clock
    2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
    3: POST bit is set following the PEND bit
    4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
    5: ISR address is posted to CPU core for branching
    6: CPU acknowledges the interrupt request
    7: ISR address is read by CPU for branching
    8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
    10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
    11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status

    The total interrupt latency (ISR execution)
    = POST + PEND + IRQ + IRA + Completing current instruction and branching
    = 1+1+1+2+7 cycles
    = 12 cycles