Yes, that is correct. Chapter 9 standard requests need no external CPU intervention. If there is a request that SX2 doesn't understand (outside of Chapter 9) it will interrupt the external CPU. After the SX2 receives a set-up packet to which it cannot respond automatically, the SX2 will assert a SETUP interrupt. After the external master reads the IRQ register to determine that the interrupt source was the SETUP interrupt, it can initiate a read request to the SETUP register, 0x32. When the SX2 sees a read request for the SETUP register, it will present the first byte of set-up data to the external master. Each additional read request will present the next byte of set-up data, until all eight bytes have been read. The external master can either stall the endpoint or respond to the control request with a data phase.
A detailed explanation on handling Endpoint 0 control packets can be found in attached SX2 datasheet.
Note: The SX2 is NRND ( not recommended for new designs)