The FIFO data bus(Port B and Port D) width is controlled by WORDWIDE bit of EpxCFG. If bit is set, data bus is 16 bit wide and otherwise its 8 bit wide. On a hard reset, the FIFO data bus defaults to 16-bit mode (WORDWIDE = 1) for all FIFOs. If all of the FIFOs are configured for 8-bit mode, Port D remains available for use as general-purpose I/O. If any FIFO is configured for 16-bit mode, Port D is unavailable for use as general-purpose I/O regardless of which FIFO is currently selected via the FIFOADR[1:0] pins.