When ASYNC bit is set to 1, the GPIF/slave FIFO interface is set in asynchronous mode. In asynchronous mode, IFCONFIG.3 = 1, the GPIF and the slave FIFO logic of the FX2 uses the internal (48 MHz) clock. In this mode the GPIF/slave FIFO runs asynchronously to the external peripheral.
If you would like the FX2 GPIF/Slave FIFO interface to be synchronized with the external peripheral (running on one and the same clock source) you must set the ASYNC bit to 0. Setting this bit to zero results in the GPIF/slave FIFO state machine relying on the IFCLK as the clock source. In other words, when ASYNC=0, the FIFO/GPIF operate synchronously: a clock is supplied either internally or externally on the IFCLK pin; the FIFO control signals function as read and write enable signals for the clock signal. When ASYNC=1, the FIFO/GPIF will operate asynchronously, no clock signal input to IFCLK is required.
Please refer to section 15.5.2 Interface Configuration (Ports, GPIF, slave FIFOs) of the FX2 Technical reference for further information on this bit setting.