The synchronous/asynchronous mode is selected by setting the the SAS Bit (Bit 6) of the READY Register. This bit effectively controls how the TDY inputs are connected to the GPIF input logic.
If SAS = 1, the RDY [5. .0] inputs are synchronous to the GPIF clock, sampled at only one rising edge of the GPIF clock.
If SAS = 0, the RDY [5. .0] inputs are asynchronous to the external clock and are sampled at two rising edges of the GPIF clock before the appropriate GPIF branch is taken.