In this case, you should:
1) Have the 8051 examine the GPIFREADYSTAT register to determine if the target FIFOs are not full.
2) Once this condition has been established, set up the GPIFTC[B1:B0] registers for 1024.
3) Check that the GPIF is idle, then launch the FIFO Read waveform, each time passing through IDLE.
4) Repeat the process for multiple 1024 block transfers.