FX2LP REVCTL Settings for AUTOMODE Operation.

Question: The FX2LP Technical Resource Manual section 9.3.4 mentions that the REVCTL bits DYN_OUT and ENH_PKT must be set to 1. But if these bits are set to 1, the FIFO cannot accept the OUT data. If these bits are set to 0, the FIFO cannot be reset well sometimes. Why should the REVCTL bits be set to 1? Is Figure 9-28 in the FX2 technical resource manual correct?

 

Answer:

It is necessary to set REVCTL bits DYN_OUT and ENH_PKT in order to enable/disable certain features in FX2LP. The features that are enabled/ disabled on setting these bits are explained in section 15.5.9 of the TRM (REVCTL register definition). If these features are not required in the application then, there is no need to set them. The TRM section 9.3.4 provides some code segments for initializing and using the FX2LP in AUTOOUT mode. These segments of code work only when the REVCTL bits are set. The segment of code provided below initializes the FX2LP to work in AUTOOUT mode even when the REVCTL bits are not set to 1.

// set the CPU clock to 48MHz 
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1); 
SYNCDELAY; 

EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered 
SYNCDELAY; 
EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered 
SYNCDELAY; 


FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from 
// host 
SYNCDELAY; 
FIFORESET = 0x02; // reset EP2 FIFO 
SYNCDELAY; 
FIFORESET = 0x06; // reset EP6 FIFO 
SYNCDELAY; 
FIFORESET = 0x00; // clear NAKALL bit to resume normal 
// operation 
SYNCDELAY; 

EP2FIFOCFG = 0x01; 
SYNCDELAY; 
EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero 
// length send, word ops 
SYNCDELAY; 
EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length 
// send, word ops 
SYNCDELAY;