The bus matching feature available on some synchronous dual-ports works a little differently than the bus matching feature in asynchronous dual-ports. The difference is in how it is set up.
Bus matching is usually available on one port to allow data going into that port be sized to fit whatever the dual-port is connected to. That means that while one port will be utilizing all 36 bits of the data bus, the other port can be configured to operate in a x9, x18, or x36 mode. When bus matching is used, only a portion of the data lines will be used.
In the bus matching mode, a number of control inputs are provided to enable the user to select the bus size as well as the order in which data is driven on the I/O pins. In the synchronous dual-ports, these pins are the BM (Bus Mode), BE (Big Endian), and SIZE (Bus Size) pins. The BM and SIZE inputs in the sync devices are used to select the bus width at which the right port will operate, i.e., x36, x18, or x9. The chart below describes the different arrangements possible:
|0||0||x36||IO0 - IO35|
|1||0||x18||IO0 - IO17|
|1||1||x9||IO0 - IO8|
BE (Big Endian) selects the order that the data will be read out. This can either be Big Endian (MSB first) or Little Endian (LSB first).
All three of these pins must be set to their wanted values during initial power-up. Normally, all three of these pins must be static throughout normal device operation. However, it is sometimes necessary to change the inputs BM, SIZE , or BE while the device is "deselected" (CE# = high). If so, these inputs must be reconfigured at least 1 clock cycle before the device is "selected" again so that the new setup can take into effect. This is not recommended, though. It is better to keep these inputs static.
For more information regarding the bus matching feature available on these dual-ports, please reveiw the application note, Understanding the FLEx36 Dual-Port SRAMs