Burst Counter Operation and chip disabled for synchronous dual port SRAM's

Version 1
    Question: If I do a read or write of a number of words and I use the internal counter (ie load the counter start address on the first word and then count after that), but I only give a CE (chip enable) every other clock; will I read data from consecutive address locations every other clock?  An example: For a burst read -- first clock load counter, second clock do nothing, third clock give chip enable and read first data, fourth clock do nothing, fifth clock give chip enable and read second data (next one in memory after first), sixth clock do nothing, seventh clock give chip enable and read third data, etc.  Note that output enable and counter enable will always be active. Could you confirm this for me?

     

    Answer:

    The counter advances based upon the rising edge of clock and not CE0# nor CE1, so in this example, assuming a free running clock:

     

                                                                                                                                                                                             
       

         Clock cycle

      
       

         Operation

      
       

         ADS#

      
       

         CNTEN#

      
       

         Internal Counter value

      
       

         1st

      
       

         Load counter

      
       

         low

      
       

         low

      
       

         --

      
       

         2nd

      
       

         Do nothing

      
       

         high

      
       

         low

      
       

         address

      
       

         3rd

      
       

         Read

      
       

         high

      
       

         low

      
       

         address +1

      
       

         4th

      
       

         Do nothing

      
       

         high

      
       

         low

      
       

         address +2

      
       

         5th

      
       

         Read

      
       

         high

      
       

         low

      
       

         address +3

      
       

         6th

      
       

         Do nothing

      
       

         high

      
       

         low

      
       

         address +4

      

    As the table above shows, you end up reading out every other word.