Timing and clock skew in synchronous Dual port during simultaneous read and write at same location

Question: What does it mean to violate tCCS when one port is writing and the other reading from the same location?  How does the timing differ depending on whether it is the read or the write that happens slightly before the other?

 

Answer:

When one port is writing and the other reading from the same location, the write operation always proceeds (the data to be written is written to the memory regardless of the simultaneous read), while the read operation timing is as discussed as below.

 

There are 2 cases to be considered during this kind of simultaneous access:

 

Case 1: The write happens clock skew time (tCCS) ahead of the read (timing diagram in datasheet)

1) When tCCS >= minimum specified value, the data can be read out (tCYC+tCD2) time after the positive edge of the read clock.
2) When tCCS < minimum specified value, the data is read one extra clock cycle later, (2*tCYC+tCD2) after the positive edge of read clock (given that all control signals are held for the read). In this case, tCCS is violated, because at the "expected" time of (tCYC+tCD2), indeterminate data (that is not necessarily either the old or the new data) is available to the read port and valid data appears only an extra clock cycle later.

 

Case 2: The read happens clock skew time (tCCS) ahead of the write

1) If tCCS >= minimum specified, the OLD data will be read out at time tCYC+tCD2 after rising edge of read clock.

2) If tCCS < minimum specified value ( that is the write occurs less than minimum specified clock skew time after the read), valid data can be read out of the read port 2*tCYC+tCD2 after the rising edge of the read clock (given that all control signals are held for the read). At time tCYC+tCD2 after rising edge of read clock, indeterminate data is across the read port.