Simultaneous access is when both ports are trying to access the same address at the same time. This can mean either reading or writing. Like asynchronous dual-ports, there are different types of simultaneous access, and depending upon which scenario is occuring, the dual-port reacts differently.
Below is the full list:
Both ports reading at the same time: This is a perfectly legal operation. Both ports can access the same address at the same time and the data read will be valid.
Both ports writing at the same time: When trying to write to the same data locaction at the same time from both ports, the integrity of the data written depends on the skew between the clocks of each port. If the skew between the two clocks is at least tCCS (defined in the datasheet), then the last data written will be valid. Otherwise, the integrity of the data written is not guaranteed.
One port reading, one port writing: Similar to the case when both ports are writing, what value is read will depend on the skew between the two port clocks. For example, if the read operation from one port occurs at least tCCS after the write operation, then the data read will be valid. tCCS is the minimum amount of skew required between right and left port operations to guarantee that the data read is successful. By successful, we mean that both the data that was writtern to the dual-port and the data read from the dual-port is the same. However, if the read operation occurs less than tCCS after the write operation, thereby violating tCCS, then the data read will either not be valid at all (CY7C08xxV) or it won't be valid for an additional amount of time (CY7C09xxx and CY7C09xxxV). This is sometimes called tCWDD. If both port clocks are tied together, you will violate the clock to clock setup tCCS. This means that you cannot write to and read from the same address at the same time. If you do so, the read data will be invalid. The write data will always successfully complete. This means that for this configuration, a read may be conducted from the same address on the cycle following the write operation.