All of Cypress' active FIFOs are built on a dual-ported SRAM memory cell structure. This means that the FIFO memory array is similar to a dual-port memory array. It is volatile, meaning that when you power off the device, it will not hold the information stored in the FIFO and it is static, meaning the data will remain in the memory as long as it is powered and does not require refreshing.
At one point in time, FIFOs were bubble-through devices that consisted of a chain of registers. However this architecture has become outdated. As you write into a bubble-through FIFO, each new word is stored into the next register. The problem is when you have written many words into the FIFO and then read out the first word. In a bubble-through FIFO, each word in the FIFO then must move up a position in the chain. This requires most of the FIFO to be re-written and causes longer and longer "rewrite" times as the FIFO depths increased.
Current FIFOs instead use pointers to manage the First In, First Out structure of FIFOs. There is a write pointer and read pointer in each FIFO that manages where the next word is written and from what location the next word is read from. Then, logic can use the relative position of the pointers to calculate the fullness of the FIFO.