When the Full Flag is asserted, all write operations are ignored. If RCLK and WCLK are tied to the same clock and the reading port is waiting for the FIFO to be full before it begins to read, you will lose two words on the writing side due to how Full Flag is designed. Remember that Full Flag is synchronized to the WCLK. When you write the last word into the FIFO, tWFF after that clock edge, /FF is asserted. On the next clock cycle, the write operation is ignored. If at the same time, the assertion of /FF triggers the other port to begin reading, that is okay. The read operation will occur, but you will lose one write operation due to the Full Flag being asserted. However, you will actually lose another write cycle due to the violation of tSKEW1. Since WCLK and RCLk are tied together, the FIFO will not de-assert the Full Flag until tWFF after another clock cycle passes. Therefore, if you are continuously writing into the FIFO at every clock edge, you will lose two words in this setup.