Parity generation during Read and Write

Question: How is parity generated during reads and write?



 In all of cypress's SRAMs, parity check logic is not implemented on the part. The parity check is upto the discretion of the user. If the user decides not to use the parity feature then, they can use the extra 4 I/O bits as data bits. For e.g.; the CY7C1347B is a 128K x 36 SRAM. So, if the user decides to include parity check feature, they will use the four bytes (8 bits each) for data and the extra 4 I/O lines for parity check. Even parity or Odd parity check has to be decided and logic to generate the parity bit in the memory controller has to be implemented. When a write is initiated, the memory controller will decide (depending on the data of the 8 bits and whether to check for even or odd parity) to write either a '1' or a '0' on the parity bit. When a read is initiated, the parity decoder logic in the memory controller will read the 8 bits coming and see whether the parity bit should be a 1 or a zero and flag if there is any discrepancy found.