SRAM Interface to Motorola 7410 Processor

Question: What are the ranges of densities that can be used for L2 Cache application with a Motorola 7410 Processor?



Any of Cypress Sync Burst Pipelined SRAMs(Single Cycle Deselect) can be used with this processor. The processor can support up to a max of 16M, i.e. two SRAMs of 8M each and each with a 256K x36 configuration as the processor supports a 72 bit bus.