Please note that K and K\ clocks are not true differential clock signals. There is no differential receiver in the SRAM. The DDR uses the rising edges of K and K\ to latch input signals. Both clocks are single ended signals. Although they are not true differential, it is advised to keep K and K\ 180 degrees out of phase with respect to one another. This effect produces the ability for the DDR to perform a double data rate one clock cycle.
For more information please refer to the application note QDR (TM)-II and DDR-II Design Guide - AN4065, which describes the different clocking strategies that can be adopted in QDRII/DDRII SRAMs and it describes each of the strategies in detail.