The SRAM has two completely independent read and write ports. With the 1302 device, you can assert both the read port enable and write port enable on the same rising edge of K. This would begin both a read and write access, at the same time. There is no delay required in this assertion.
When you begin a read and write access at the same time, you would need to give the address for the read access at the same time (rising edge of K). Then, on the falling edge of K, you need to give the address for the write. This style of pipelining allows you to begin read and write accesses at the same time with only one address bus.