Cypress has a development kit (CY3688) for connecting the , into a design, but Cypress do not have a reference design for creating the SIE logic that interfaces with the CY7C68003 transceiver. This is not a trivial task, and is usually undertaken by peripheral IP vendors such as Mentor graphics, Synopsys, etc., or ASIC vendors who want further integration.
Mentor graphics has a USB 2.0 VHDL core (MUSBHSFC):
Synopsys also has a USB 2.0 core:
The SIE logic should be designed to the UTMI spec version 1.05, which can be downloaded at: