Reference design for CY7C68003 TX2UL

Question: Does Cypress provide a reference design on how to drive the UTMI interface?

 

Answer:

Cypress has a development kit (CY3688) for connecting the , into a design, but Cypress do not have a reference design for creating the SIE logic that interfaces with the CY7C68003 transceiver. This is not a trivial task, and is usually undertaken by peripheral IP vendors such as Mentor graphics, Synopsys, etc., or ASIC vendors who want further integration.

Mentor graphics has a USB 2.0 VHDL core (MUSBHSFC):

http://www.mentor.com/inventra/usb-otg/

Synopsys also has a USB 2.0 core:

http://www.synopsys.com/products/designware/docs/ds/c/dwcore_usb2_device.html

http://www.synopsys.com/news/pubs/dwtb/q102/dwtb6_sec3.html

The SIE logic should be designed to the UTMI spec version 1.05, which can be downloaded at:

http://www.intel.com/technology/usb/download/2_0_Xcvr_Macrocell_1_05.pdf