The SAS bit in GPIFREADYCFG controls how the RDY signals connect to the GPIF input logic. If the internal IFCLK is used to clock the GPIF, the RDY signals can make transitions in an asynchronous manner, i.e. not referenced to the internal clock.
Setting SAS=1 causes the RDY inputs to pass through two flip-flops for synchronization purposes. If the RDY signals are synchronized to IFCLK, and obey the setup and hold times with respect to this clock, the user can set SAS=0, which causes the RDY signals to pass through a single flip-flop.
For more infomation on register settings refer the ez-usb technical reference manual in the link www.cypress.com/?rID=38232