Users seeing this issue likely have two user modules with the same default pin selections and parameters. When you updated your user module, PSoC Designer reverted the pin parameter selections to their default settings. This is a known issue with PSoC Designer and could impact any project that contains the combination of user modules below. Note that some of the example projects included with the CY3280 series CapSense kits also exhibit this issue.
- Any CapSense (CSD, CSD2x, CSDADC, SmartSense, SmartSense_EMC)
To work around this error please review the Pinout window after updating your User Modules to ensure that the parameter selections are correct. For example, assume your project contains both a CSD and an EZI2C user module. If you update the CSD user module to the latest version, the drive modes for the EZI2C SDA and SCL pins will change to “High Z analog”. The drive mode for the CSD Modulator Capacitor Pin will change as well. To solve this issue you would change these drive mode settings back to their original values, regenerate your project, and rebuild.
PSoC Designer 5.1 SP3, which is scheduled to be released in early Q4 2011 will deliver a permanent fix for this defect. If this Knowledge Base Article did not address your issue please contact technical support so we may further assist you.