Burst Operation for Single Data Rate Synchronous SRAMs - KBA80730

[Anonymous]

Version: **Question: How does the burst feature work in Standard Sync/NoBL SRAMs (single data rate synchronous SRAMs)?Answer:

For each address input, the SRAMs can provide data from up to four address locations. The result is a four-fold increase in the amount of data obtained by a single address call and a commensurate reduction of the activity on the address bus.
 

Burst Operation in Standard Sync SRAM
 

Standard sync SRAM has Advance input signal (ADV#), sampled on the rising edge of Clock. When asserted, it automatically increments the address in a burst cycle. Figure 1 represents the waveform for burst operation in standard synch SRAM. A single address is presented to the device (shown in the figure as an Address A(0)), from which the Data I/O produces the first data (DA(0)). Asserting ADV# LOW latches the signal at the next clock rise and automatically increments the burst counter to the next address in the burst sequence. According to Linear or Interleaved mode, the predefined sequence of data (DA(1), DA(2), DA(3)) from the respective addresses are accessed on subsequent clocks.
 

Figure 1. Burst Operation in Standard Sync SRAM


 

Burst Operation in NoBL SRAM
 

NoBL SRAM has Advance/load input (ADV/LD#), used to advance the on-chip address counter or load a new address. When asserted HIGH, the internal burst counter advances. When asserted LOW, the device can load a new address. After deselection, the ADV/LD# should be driven LOW to prepare it to load a new address. Figure 2 represents the waveform for burst operation in NoBL SRAM. A single address (A(0)) latches to the device when ADV/LD# is LOW, from which the Data I/O produces the first data (DA(0)). Asserting ADV/LD# HIGH latches the signal at the next clock rise and automatically increments the burst counter to the next address in the burst sequence. According to Linear or Interleaved mode, the predefined sequence of data (DA(1), DA(2), DA(3)) from the respective addresses are accessed on subsequent clocks.
 

  Figure 2. Burst Operation in NoBL SRAM
   

 

Burst Functionality in Standard Sync SRAM
 

The address and control pins latch to the SRAM on the rising edge of the input clock (CLK). All accesses for standard sync SRAMs initiate the same way. Depending on the control signals, the SRAM initiates a read or write transaction. On the next rising edge of the clock, it samples the ADV# pin. If ADV# asserts LOW, the SRAM initiates a burst access and continues the present operation with an address obtained from the internal counter. This internal counter is a 2-bit burst counter that can access four address locations.

The burst continues until the ADV# pin is active or the SRAM starts a new cycle. If the ADV# remains active without introduction of a new input address, then the SRAM wraps around to the originally accessed address location, as shown in Figure 3. If the new address arrives during the burst operation, then the SRAM holds it for the next burst process, until the completion of the present burst operation. The SRAM works in the normal mode if the ADV# pin is inactive and the data I/O produces data with respect to the current address only.
 

Figure 3. Burst Mode Address Update
 

NoBL SRAM updates the addresses same way as Standard Sync SRAM, with ADV/LD# pin functionality.