Burst Operation for QDR and DDR Synchronous SRAM Families - KBA80731

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Question: How does the burst feature work in QDR and DDR SRAMs, and what are its advantages?



The QDR and DDR family of devices operate on a principle of burst data outputs. The memories have an option of a Burst of 2 or a Burst of 4.
  At the outset of a memory read cycle, the memory controller presents an address to read from the memory. This address, along with the appropriate Read Control Signal, is latched in to the memory at the rising edge of K Clock. The data then appears on the outputs after a set number of latency cycles. The latency depends on the part selected. The expected data appears at the rising edges of K and Kb clocks. With the Burst of 2 option, device data is sent to the outputs from the address and the next higher address location. With the Burst of 4 option, the next three higher address location data is sent on the appropriate edge of the clock output. With 2 Word Burst, the data appears at the rising edge of K and the immediately next rising edge of Kb. In other words, the data is at the output within a single K clock cycle. With 4 Word Burst, the data appears at K followed by Kb and then the next K and its corresponding Kn. The data read transaction is complete in two K Clock Cycles for a Burst of 4.

  In these SRAMs, there are multiple, separate memory banks: two for Burst of 2 and four for Burst of 4. The memory locations are accessed from each of the banks for a given address. For example, the CY7C1425 has two memory banks each of size 2M x 9. When provided one 21-bit address, it accesses a memory location in each bank.[1] Thus, to access this 4M x 9 memory, you need 21 address lines instead of 22.

For more information, see the product datasheet:

  •    Burst Operation – In the Functional Overview, review the Read Operations section.
  •    Operation of QDR and LD# Part – Review the Pin Descriptions of RPS, WPS, and BWS.
  •    Operation of DDR Family Part – Review the Pin Descriptions of R/W# and BWS.
Advantages of burst operation in QDR/DDR Sync SRAMs:

  •    Reduced activity on the address bus (four memory locations accessed with a single address)
  •    Address generation to the SRAM to free the controller to perform other functions

[1] 2^21 = 2M