1. This auto increment burst from FPGA won’t work if burst operation is required in the SRAM.
For SRAM burst, ADV/ pin should be asserted low and the Mode pin should be selected accordingly for linear or interleaved burst.(Needs to be modified)
2. The BWS/ (a,b,c,d) are used for selecting the bytes to which data needs to be written.
If writes need to be masked. BWS/ should be asserted HIGH (disabled) and GW/ should be HIGH.
3. Yes, it is possible to have ADSP/ and ADSC/ permanently asserted. ADV/ if asserted low always will set the SRAM in burst mode.