Question: What are the design constraints in the interchangeability of data and address pins in Sync SRAMs?
Answer: The freedom to assign bit order in SRAM devices is possible due to memory technology that does not require row and column addressing or any refresh or charging delays. There are, however, a few constraints to follow as described in the following sections:
Sync/NoBL SRAMs
The address pins (A) in Sync NoBL SRAMs can be assigned to any address bit in any order. Two address inputs (A0) and (A1) connect to the linear burst counter and must be connected to the lower order address bits.
The data pins (DQ) also can be assigned in any order, but they must adhere to a Byte Enable grouping. These pins are grouped by letter DQa, DQb, DQc, or DQd that corresponds to BWa, BWb, BWc, and BWd.
The parity pins (DQP), if present, are grouped with the data pins (DQ) as DQPa, DQPb, DQPc, and DQPd. These are simply extensions of the data pin group and are also controlled by the corresponding group Byte Enable.
Please refer to AN4025 for a detailed explanation using a Sync/NoBL SRAM.
DDRII/II+ and QDRII/II+ SRAMs
The address pins (A) in DDRII/II+ and QDRII/II+ SRAMs can be assigned to any address bit in any order. For DDRII SRAMs, two address inputs (A0) and (A1) connect to the linear burst counter and must be connected to the lower order address bits. DDRII+ and QDRII/II+ SRAMs do not have the linear burst counter.
For CIO (Common I/O) DDRII/II+ devices, the data pins (DQ) also can be assigned in any order, but they must adhere to a Byte Enable grouping. Within a Byte Enable group, DQn may be connected in any order.
For SIO (Separate I/O) DDRII/II+ devices and all QDRII/II+ devices, the data input pins (D) and output pins (Q) can be assigned in any order as input/output pairs, but they must adhere to a Byte Enable grouping. Within a Byte Enable group, Dn may be connected to any bit of the input data bus as long as Qn is connected to the corresponding same bit of the output data bus.
