Data Valid Window Calculation

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    Question: How do you calculate the Data Valid Window in QDRII SRAMs?



    Data Valid Calculation mentioned below is when echo clocks(CQ, CQ#) are used for read capture.


    The formula for calculating data valid window is tCQHCQ#H -tCQD+tCQDOH.

    The switching parameters are defined below:


    tCQHCQ#H - CQ clock rise to CQ clock rise  (rising edge to rising edge) [This parameter is extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). It is only guaranteed by design and is not tested in production.]    

    tCQD - Echo clock high to data valid

    tCQDOH - Echo clock high to data invalid

    For eg: Data Valid WIndow for the 65nm part CY7C1511KV18 at 300MHz, DVW = 1.4-0.27-0.27=0.86ns


    Also the tKHK#H parameter calculation differs for 90nm and 65nm parts and the formula is different as indicated in their respective datasheets.