Translation - Japanese: nvSRAMのWE#端子へのプルアップ抵抗 - KBA83047 - Community Translated (JA)
Why do you need to connect a pull-up resistor on the WE# control line of an nvSRAM? What should be the value of the pull-up resistor? Why does one particular location of nvSRAM get corrupted whereas all the other locations store and restore data normally?
The nvSRAM is normally connected to a microcontroller or a microprocessor I/O in an application. Many microcontrollers and processors tristate their I/Os during their boot up sequence. These I/Os are configured anywhere from a few milliseconds to a few hundred milliseconds after power cycle, depending on the application processor. The nvSRAM takes about 20 ms for its RECALL operation, after which the nvSRAM is ready for normal access. If the processor I/Os are not up within 20 ms, and if the tristated CE# and WE# lines pick up a logic zero state, a write operation is initiated in the nvSRAM. In this case, whatever logic levels are present on the nvSRAM's address lines will be picked up by the device, causing random data to be written in that particular address location. To protect the nvSRAM, pull up the WE# line using an external pull-up resistor with a value between 5.6KΩ and 10KΩ.