The two most important parameters are the transmitter gain (TX_Gain) and receiver gain (RX_Gain). The best transmitter gain depends on the external transmit circuitry. If using the high-voltage reference design (CY3272, CY3274) the gain should be set to 480mVp-p (TX_Gain = 0x07). If using the low-voltage reference design (CY3273, CY3275), the gain should be set to 1.55Vp-p (TX_Gain = 0x0b). The reason for the difference is that the high-voltage reference design has more amplification external to the device. Note that for CENELEC compliant designs using the high-voltage reference design, the system was tested to be compliant with a gain of 125mVp-p (TX_Gain = 0x03).
The receiver gain should be set to 125uVrms sensitivity (RX_Gain = 0x07) for all reference designs. This will provide the best sensitivity in the majority of powerline environments. A lower receiver gain may help slightly if there is a large amount of noise in the 125 - 145kHz range.
Additional settings that may provide a slight improvement in performance are lowering the Baud Rate from 2400bps and increasing the Transmit Delay from 7ms. If testing with 1200bps (Modem_BPS_MASK = 0b01), the Transmit Delay must be set to >=12ms (TX_Delay != 0x00). If testing with 600bps (Modem_BPS_MASK = 0b00), the Transmit Delay must be set to >=18ms (TX_Delay = 0b10 or 0b11).
The FSK Bandwidth (Deviation) should be set to 130.4kHz - 133.3kHz (Modem_FSK_BW_MASK = '1').
If using the CY8CPLC20, setting the CPU frequency to 24MHz (Sysclk/1) will give the best performance.
If using the CY8CPLC10 device, refer to the CY8CPLC10 data sheet for more details on setting these parameters. If using the CY8CPLC20 device, refer to the Powerline Transceiver (PLT) User Module data sheet for more details on setting these parameters.