Internal to the part there are two latches, an address latch and a data latch.Which one is read and written to depends on the A0 line. If you are reading back the register address then you are accessing the Address register when you read.
Check the following:
1) On the read cycle you still have a 65ns A0 setup time referenced to the rising edge of the RD strobe. (the RD/WR strobe has a required 65ns hold time so theoretically you could toggle both at the same time and be okay).
2) Most of the time this problem occurs because the cycle time between accesses is violated (remember writing the register address is an access). Be sure that nCS inactive time (Tcscs) of 85ns is met (also twrrdl which is 85ns. nWR high to nRD low). Therefore between writing the register address and reading back the data you need to allow 85ns.