No, a single read or write to the Dual Ported memory without any arbitration cycle should not generate additional wait states. As mentioned in the Knowledge Base article titled "PCI-DP Local Bus Wait States and Resource Access Arbitration", the PCI-DP exhibits a fixed number of wait states for access to it's Dual-Port memory.
The number of wait states for a Dual-Port memory access is two CLKIN cycles from detection of the start of the basic transaction, (both SELECT# and STROBE asserted). All subsequent dataphases will burst continuous with zero wait states unless either of the Ready In signals is deasserted or, and only for the case of reads, the 64-byte boundary is crossed (which inserts one wait state to the read access).
The number of wait states for any other access (not to the Dual-Port memory) is two CLKIN cycles from detection of the start of the basic transaction, (both SELECT# and STROBE asserted), if there is no resource contention with the PCI bus interface. If the PCI bus is accessing any of these resources regardless of specific register or FIFO, then additional wait states will occur until the PCI transaction completes.