Clearing interrupts in the Host Interrupt Event Status Register

Question: - How do I clear interrupts in the Host Interrupt Control and Status Register?  - How do I clear interrupts in the Local Processor Interrupt Control Status Register?

 

Answer:

There are two status registers in the Operations Register space of the PCI-DP: one for the local processor, one for the PCI host. The Host Interrupt Control and Status Register (HINT) is located at address offset 0x04E4. The Local Processor Interrupt Control Status Register (LINT) is located at address offset 0x04F4. Initially, all the interrupt status bits are cleared. When one of the interrupts is enabled, writing a 1 will clear the interrupt, except bit 6 and 7.