Question: I used pin 15[6]/[7] as ‘strong’, ‘initial state low(0)’ digital output. But why these two pins' initial output state is high instead of low when PSoC works?
Answer: All of the DR registers (Except PRT15_DR) in PSoC3 are reseted to low, but the PRT15_DR register for the DP and DM pins is reseted to high. This is the reason lead to the problem. But the influence is only limited to the initial output state of P15[6]/P15[7], you can change the state of the two pins in the application program(for example: main.c) freely just as other GPIOs. If you need to ensure the initial state of 15[6] /15[7] is low after reset, please use the method below:
- Build the project successful after your design is done.
- Add program 'CY_SET_REG8((void CYXDATA *)(CYREG_PRT15_DR), 0x00);' before program 'CY_SET_REG8((void CYXDATA *)(CYREG_USB_USBIO_CR1), 0x20);' in the cyfitter_cfg.c
- Build the project again.
If you need to change any part of your design later, the above three actions should be done step by step again after the change.
