These can be made by clocking both the read and write ports of a single FIFO with the same clock. The key to proper operation is that you need to fill the FIFO completely before you start read operations. From a reset state, each write clock writes a full character into every location. Of these writes, only the lowest order bit is valid, but until the FIFO fills, this is a don't care. Just short of full (possibly one clock cycle on either side of this to match up the piplineing delays), you start reading data and writing data on each clock cycle.
The FIFO never goes empty, and never goes full, because both a read and a write occur on each clock cycle. The entire device becomes one long, fully-synchronous shift register. In addition, you have access to the shift register at multiple taps in the middle of the chain; one at each data bit position in bus width of the FIFO.
For example, a 36-bit SYNC FIFO, configured as described, would have 35 taps in the middle of the delay path, plus the output at the end of the chain. This type of delay with taps is very useful in video processing. For example, if you use a counter to set the initial delay before reads start, each tap can be exactly one scan-line apart. This allows things like scan doublers and interpolators to be built that generate intermediate images by averaging the pixels from the line above and the line below the one being added to the frame. The exact same thing can be done with a dual port, but the built-in addressing in the FIFO's makes it much simpler to implement.