Programmable flags are provided to allow the designer to control overflow and underflow. Each flag can be programmed to any value from 1 to the depth of the FIFO (i.e. a 1K x 8 FIFO can be programmed to any value between 1 and 1024). However, the Programmable Almost Full flag (PAF) is counted backwards. So if you set the PAF to 5, it will assert when there are 5 or less spaces left (1019 or more words in a 1K FIFO). If the values for the PAE and PAF flags are NOT programmed on startup, the default value of 7 will be used for both.
Programming the PAE and PAF values is done during startup. The proper method is slightly different for different FIFO families, but normally it is done with a LD (load) pin. The exact method is described on each part's datasheet. For example, in the CY7C42x1 FIFOs, when WEN2/LD# is held LOW during Reset, this pin is the load enable for flag offset programming. Right after power up, the designer can send the offset value on the input data bus and these values are stored in the offset registers. If the Almost Empty and Almost Full flags are not going to be used (or default values are going to be used), then WEN2/LD# can be tied high.
In addition, because the offset values are usually programmed via the data bus, the number of available spaces versus the number of total bits needed to set the offset usually do not match perfectly. In this case, the unused spaces are ignored. For example, with the CY7C4201 256 x 9 FIFO, each programmable flag can be set to any value between 0 and 255. This only requires 8 bits. The data bus is 9 bits. Therefore, the most significant bit of the offset register is ignored. When read back, it will be read as 0.
Finally, some synchronous FIFOs have a partial reset and a master reset. Partial reset allows you to clear the memory and move the pointers back to the first location without losing the PAE and PAF register values. Otherwise, a master reset will clear those registers as well.