Address pins in burst 4 mode of QDR SRAMS

Question: How the address pins of QDR SRAMs are assigned, which pin is high bit, and which pin is low bit on the address bus?



Typically in a burst SRAM ( Std Sync and NoBL) , the LSB and MSB do matter because they are the address bits that are increased when bursting.

This is different, however, on the QDR devices with burst of 4 option. For this device because every read or write access has to be a burst of 4 operation, the 2 least significant bits are actually internal to the device. This is why for a 512K x 36 memory size; you only need 17 address bits (as opposed to 19 bits to access the entire 512K). The memory array is internally organized as 4 arrays of 128K x 36 each. Each read/write operation read or writes into the same location in all 4 arrays.

Address numbering (A0, A1, etc) is not necessary because the burst address bits (A0, A1) are internal to the device.