Make sure that all the voltage pins, Programming pins, reset pins are connected appropriately. Following are hardware connections to be looked into.
Vdda:- (1.8 V ≤ VDDA ≤ 5.5 V) Supply for all analog peripherals and analog core regulator. Vdda must be the highest voltage present on the device. All other supply pins must be less than or equal to Vdda. 0.1uF capacitor should be connected between this pin and Vssa.
Vddd:- Supply for all digital peripherals and digital core regulator. Vddd must be less than or equal to Vdda. A 0.1uF capacitor should be connected between this pin and Vssd.
Vssa:- Ground for all analog peripherals.
Vssb:- Ground connection for boost pump.
Vssd:- Ground for all digital logic and I/O pins.
Vddio0, Vddio1, Vddio2, Vddio3:-Supply for I/O pins. Each Vddio must be tied to a valid operating voltage (1.8 V to 5.5 V), and must be less than or equal to Vdda. If the I/O pins associated with Vddio0, Vddio2, or Vddio3 are not used then that Vddio should be tied to ground (Vssd or Vssa). A 0.1uF capacitor should be connected between each Vddio pin and Vss.
Vcca:- Output of analog core regulator and input to analog core. Requires a 1-μF capacitor to VSSA. Regulator output not for external use.
Vccd:- Output of digital core regulator and input to digital core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1-μF capacitor should be connected between one of the Vccd pin to VSSD.
See the PSoC3 datasheet to connect them appropriately. Also make sure that you have connected appropriate value capacitors to all these pins, the description of which can be seen under Power System in Psoc3 Datasheet.
Also Make sure that the following 5 pin required for programming on the JTAG interface are properly connected.
XRES (and configurable XRES):-External reset pin. Active low with internal pullup. In 48-pin SSOP parts, P1 is configured as XRES. In all other parts the pin is configured as a GPIO.
TCK:- JTAG test clock programming and debug port connection.
TDI:- JTAG test data in programming and debug port connection.
TDO:-JTAG test data out programming and debug port connection
TMS:-JTAG test mode select programming and debug port connection
Please refer to the Application note AN61290 (http://www.cypress.com/?rID=43337) for further detail on PSoC3 and PSoC5 Hardware Design Considerations.