FX2LP Pin States during RESET condition

Version 1
    Question: What are the states of the pins during RESET condition?

     

    Answer:

    The state of the pins of FX2LP during Power On Reset (Register bit CPUCS.0 resets the CPU. This bit is set to ‘1’ at power-on, initially holding the CPU in reset ) and when the FX2LP is held in reset (RESET# asserted) are as follows:


    1.Hard Reset Condition:
    Once the device is configured doing a hard reset (asserting RESET#) will result in the GPIO pins in the following state:

    PORTA-PORTE:         Retain its configuration/state as was set by the 8051 prior to the  RESET
    Dedicated CTL pins: Retain its configuration/state as was set by the 8051 prior to the RESET
    SCL/SDA:                    Tristate
    IFCLK:                          Retain its configuration/state as was set by the 8051 prior to the RESET
    CLKOUT:                     Retain its configuration/state as was set by the 8051 prior to the RESET
    BRKPT:                        Low, 0
    DATABUS:                   Tristate
    TXD0/1:                        Low, 0
    RD#/WR#/CS#/OE#/PSEN#: 1
    ADDR:                          0

    2. POR condition:
    Following is the state of GPIO pins during only power on reset (POR) condition:


    PORTA-PORTE:         Tristate
    Dedicated CTL pins: LOW, 0
    SCL/SDA: if done booting: Tristate
    IFCLK:                          Tristate
    CLKOUT:                     Driven/wiggling
    BRKPT:                        LOW, 0
    DATABUS:                   Tristate
    TXD0/1:                        LOW, 0
    RD#/WR#/CS#/OE#/PSEN#: HIGH, 1
    ADDR:                          LOW, 0