/BUSY Signal in Dual Port SRAMs

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    Question: /BUSY signal functionality in Dual Port SRAMs



    The Asynchronous dual port devices allow simultaneous access of the memory locations. Such simultaneous accesses may lead to memory access collisions. In such cases, if one of the ports is writing and the other port is reading, data coherence is not guaranteed, i.e. the port performing a read could receive new data or old data.

    Hence, collision detection circuitry is incorporated into the dual port devices to ensure data coherence. The circuitry detects such simultaneous accesses to the same memory location, arbitrates to picks a winner and also notifies the loser of the arbitration.

    The /BUSY signal is the notification to the losing port (writing or reading) which indicates that either the write has failed or the value read is stale. The waveform below shows the left port attempting a read on a location which is being written by the right port.

    The /BUSYL signal is driven low to indicate that the left port lost the arbitration. Once this signal is deactivated, valid data is read from the same location.

    If the losing port was attempting a write to the memory location – the dual port will block the write until the /BUSY signal is de-activated.