Using DMA to transfer data to SPIM of PSoC 3/5 on TX_FIFO_NOT_FULL flag

Question: SPI Master + DMA (rising edge trigger) configured to work on TX_FIFO_NOT_FULL flag is transmitting only the first data. Why?

 

Answer:

DMA is configured to write data into SPIM Tx buffer when TX FIFO is not full so that SPIM can start the transfer. TheTopDesign looks like:

Following is the configuration of SPIM:

DMA is configured for Edge Triggered (Rising edge) mode of trigger.

The condition that you are checking is TX_FIFO_NOT_FULL.

1) Before the SPI is initialized the signal is 0.
2) Once the SPI is initialized this signal goes high since the FIFO has 0 items in it, so certainly not full.
3) This triggers the DMA since it sees the rising edge.
4) DMA delivers a single byte to the SPI FIFO. The TX_FIFO_NOT_FULL signal is still high since it is still not full. It will stay high forever since the FIFO is never going to become full. It will either have one item from this single DMA or it will have 0 items once this one is transmitted.
5) Since the DMA is looking for a rising edge and TX_FIFO_NOT_FULL is going to stay high, no more DMA transfers will happen.

If instead you take the case of level triggered:

1) Before the SPI is initialized the signal is 0.
2) Once the SPI is initialized this signal goes high since the FIFO has 0 items in it, so certainly not full.
3) This triggers the DMA to keep sending bytes until the FIFO becomes full. This will likely result in 5 transfers. 4 to fill the FIFO and 1 additional one since the SPI will pull the first one out immediately.
4) At this point each time the SPI pulls a value out of the FIFO the TX FIFO will become not full and the DMA will immediately refill it.

 

So the right configuration for DMA to work is Level Triggered mode.