Question: What are the types and functions of burst modes in Standard Sync/NoBL SRAMs (single data rate synchronous SRAMs)?
Figure 1. SRAM Address Block
Linear Burst: The device operates in the linear mode when the user sets the Mode pin to LOW. The internal counter increases in a linear fashion from the present value with A1 and A0 as the LSBs.
Table 1. Linear Burst Mode
Interleaved Burst: The device operates in the interleaved mode when the user sets the Mode pin to HIGH. In Interleaved mode, the counter follows a pattern based on the initial value. The pattern is mainly to address Little Endian and Big Endian Byte orders. For our example in Table 2, we declare two pairs of memory locations: 00-01 & 10-11. The counter follows a pattern after each increment based on the lowest two bits of the initial value loaded into it. The counter first changes to the counterpart of the pair. For example, if the first value is 10, the next will be 11. If the first value is 11, the next will be 10. If the first value is 01, the next will be 00. After that, the counter accesses the values in the other pair in the same order as the first. So if in the first two accesses, the sequence is from higher to lower (e.g. 11 to 10), the next will be 01 to 00 and vice versa.
Table 2. Interleaved Burst Mode
For general operation, one burst method does not have any significant advantage over the other. Different processors support different types of burst operation. While the Intel processors support the interleaved burst mode, The power PC microprocessors support the linear burst mode.