Back to Back Write in Synchronous SRAMs - KBA82781

Version 2

    Version: *A


    Translation - English:



    Can /WE be kept LOW during back-to-back write operations or does it have to be toggle on every write operation in Synchronous SRAMs?



    Yes, you can keep the /WE low during back-to-back write operations. There is no problem in doing so.


    For Sync SRAMs, Write operation happens when a LOW is detected on the rising edge of the sampling clock, as against a /WE pulse in Async SRAMs. So, for back-to-back Write operations, /WE can be kept LOW.