Why is there a delay between successive bytes when the SPIM_PutArray API is used?
When the SPIM_PutArray API is used in the SPI master component, it only calls the SPIM_WriteTxData internally multiple times. This function is blocking in nature; which means that it continuously checks the space in the transmit FIFO and writes to it only when there is space.
Now, when data rate of SPI is very high, there is not enough time for the CPU to keep up the speed with the SPI master’s throughput, especially when the CPU is running on lower clock rates or the code optimization level is low. In this situation, when the SPI master completes transmission of one byte of data, the next byte is yet to be written in its transmit FIFO. Therefore, there is a delay until that byte is written to the FIFO.
One method to overcome this issue is the use of DMA to transfer data from the memory array to the SPI master.