When I reset an FX2LP using the external RESET# pin with an erratic signal, the chip fails to reset as expected. It also fails subsequent external resets with a proper reset signal. The correct functionality resumes when the whole device is power cycled again. What causes this behavior and how can I avoid it in a design?
When FX2LP fails to reset, check whether the SCL/SDA lines of FX2LP are LOW. When these lines are forced HIGH, FX2LP resets with a proper reset signal.
When you apply an erratic RESET# signal, FX2LP exits the Reset mode and immediately starts to communicate with the EEPROM. In this case, the SCL/SDA may go LOW or HIGH intermittently. When RESET# is asserted again (due to the presence of the erratic signal), the SCL/SDA remains LOW and FX2LP does not enumerate. As a result, when these lines are externally forced HIGH, FX2LP resumes as expected.
Cypress recommends that you connect the reset circuitry of the FX2LP RESET# pin to the EEPROM RESET/POWER pin. This resets the EEPROM each time there is a reset on FX2LP, which in turn resets the SCL/SDA lines to HIGH. This eliminates any erroneous state on these lines.