32-bit GPIF Interface failing at 100 MHz - KBA84082
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Apr 29, 2013
07:48 AM
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Apr 29, 2013
07:48 AM
Version: **
Question: Why does the 32-bit GPIF interface fail at 100 MHz?
Answer:
There are several possible reasons:
- When you call the CyU3PGpifSocketConfigure() API, the ‘burst’ parameter must be greater than 0.
- If you are using the internal clock, the clkDiv parameter of pibclock must be set to 4.The default value in SDK is 2.
- Make sure the setSysClk400 parameter is set. The FX3 master clock is set to 384 MHz by default when you use a 19.2 MHz crystal or clock source. This frequency setting may lead to DMA overflow if the GPIF is configured as 32-bit wide and running at 100 MHz. Setting this parameter will switch the master clock frequency to 403.2 MHz during the CyU3PDeviceInit() call.
- The following code must be in main () to initialize the device
CyU3PIoMatrixConfig_t io_cfg;CyU3PReturnStatus_t status = CY_U3P_SUCCESS;CyU3PSysClockConfig_t clkCfg = {CyTrue,2, 2, 2,CyFalse,CY_U3P_SYS_CLK};
/* Initialize the device */status = CyU3PDeviceInit (&clkCfg);if (status != CY_U3P_SUCCESS){goto handle_fatal_error;}
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