Translation - Japanese: PSoC 4 での時間周期測定 - KBA87496- Community Translated (JA)
How do you measure a time period using PSoC® 4?
Many applications require measurement of the time interval between two events. In PSoC 4, you can use the timer, counter, pulse-width modulator (TCPWM) counter’s Capture function to measure a time period.
The example project attached with this article shows the measurement of the time interval between the two consecutive falling edges, which can be generated by button pressing events. The GlitchFilter irons out the glitch introduced by pressing a mechanical button to improve the demo experience. It can be saved if you are measuring a signal edge, which has no glitch. See Figure 1 for a screenshot of the schematic.
For more information on the underlying principle, see the PSoC 3/ PSoC 5LP knowledge base article Time Period Measurement.
Figure 1. Example Project Schematic
Table 1 lists the Components used in this example project.
Table 1. Components Used
|Instance Name||Component Name||Component Category||Comments|
|Counter||Timer Counter (TCPWM mode)||Digital > Functions||Configured as up counter with rising edge capture.|
|UART||UART (SCB mode) for the following families: PSoC4000S, PSoC 4100/4200 PSoC 4100M/4200M PSoC4200L PSoC 4100BLE/ 4200BLE||Communications||Transmit to PC the time interval between two events. Configuration is as follows: Baud rate: 115200; Data bits: 8; Parity: None; Stop bits: 1. Any serial port viewer can be used to view the time value.|
|Software Transmit UART for the PSoC 4000 family||Communications||Transmit to PC the time interval between two events. Configuration is as follows: Baud rate: 115200; PinAssignmentMethod: Static Any serial port viewer can be used to view the time value.|
|Pin_InputSignal||Digital Input Pin||Ports and Pins||Digital pin for the signal input|
|ISR_Counter||Interrupt||System||Interrupts on capture and terminal count of the Counter|
|Clock_C||Clock||System||Configured for 3 MHz, as Counter component clock. Improve precision with a higher clock frequency.|
|Clock_G||Clock||System||Configured for 1 kHz, as GlitchFilter component clock.|
|0||Logic Low ‘0’||Digital > Logic||Configured for 3 MHz. Improve precision with a higher clock frequency.|
|GlitchFilter||Glitch Filter Only for the following families: PSoC 4200 PSoC 4200M PSoC 4200L PSoC 4200BLE||Digital > Utility||Configured for 3 MHz. Improve precision with a higher clock frequency.|
Note: For device families that do not have a glitch filter, remove the GlitchFilter and its related components, and hook the Pin_InputSignal terminal directly to the capture terminal of the Counter component. In this case, if you need to filter the possible glitches in your application, you must leverage some other method, such as firmware processing.
The example project is for the PSoC 4200 device family and designed based on the CY8CKIT-042 kit. It was verified on PSoC Creator™ 3.2. You can use the PSoC 5LP USB-UART Bridge in the kit to view the UART output. Refer to the kit guide for information on how to use the built-in USB-UART Bridge. The implementation for the other PSoC 4 device families is similar; choose the corresponding kit for different device families.
You can use a serial port viewing program, such as HyperTerminal, to view the UART output. Figure 2 shows the configuration settings required for this project. Figure 3 shows the expected UART output.
Figure 2. HyperTerminal Configuration Settings
Figure 3. Expected UART Output